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<div>The Fourth International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing and AI (CGRA4HPCA).</div>
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<div> ----------------------- GENERAL INFORMATION -------------------------</div>
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<div>CGRA4HPCA 2025 will be held in conjunction with IPDPS 2025 in Milano, Italy, on June 3rd.</div>
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<div>Where: Milano, Italy</div>
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<div>When: June 3rd</div>
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<div>Website: http://cgra4hpc.podobas.net/</div>
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<div>Submission Link: https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=CGRA4HPCWorkshopFullSubmission&site=ipdps2025</div>
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<div>Important Deadlines</div>
<div> Paper submission: February 1st, 2025 </div>
<div> Paper notification: February 23rd, 2025</div>
<div> Camera-ready due: March 6th, 2025</div>
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<div>-------------------------- DESCRIPTION ------------------------------</div>
<div>Coarse-grained reconfigurable arrays (CGRAs) are programmable logic devices that offer plasticity/reconfigurability, albeit at a coarse-grained (word-configurable) level in comparison to fine-grained FPGAs. </div>
<div>Such reconfigurability allows the silicon to be specialized towards a particular application in order to reduce data movement and improve performance and energy efficiency. Unlike their cousins, the Field-Programmable Gate Arrays (FPGAs),</div>
<div> CGRAs provide reconfigurable Arithmetic Logic Units (ALUs) and a highly specialized yet versatile data path. This ``coarsening'' of reconfiguration allows CGRAs to achieve a significant (custom ASIC-like) reduction in power consumption and</div>
<div> increase in operating frequency compared to FPGAs. At the same time, they remedy and overcome the expensive von Neumann (instruction-decoding) overhead that traditional general-purpose processors (CPUs) suffer from. In short, CGRAs</div>
<div> strike a seemingly perfect balance between the reconfigurability of FPGAs and the performance of CPUs, with power-consumption characteristics closer to custom ASICs.</div>
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<div>The International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing and AI (CGRA4HPCA) aspires to provide a recurring forum for HPC experts and CGRA hardware researchers from academia or industry to come together and
discuss state-of-the-art CGRA research for use in emerging HPC systems and AI.</div>
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<div> ----------------------- TOPICS OF INTEREST -------------------------</div>
<div>Topics of interest include (but are not limited to):</div>
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<div>- Novel high-performance CGRA architectures for HPC and AI, including energy-efficient architectures(incl. asynchronous/clockless CGRAs, power-consumption optimizations, etc.)</div>
<div>- Parallel programming language support for programming CGRA architectures (e.g., supporting OpenMP or CUDA/HIP for programming CGRA architectures)</div>
<div>- Compilation strategies, algorithms, and methods for mapping computations and applications onto CGRAs</div>
<div>- Smart middleware and runtime systems for support of CGRAs, including multi-CGRA systems for HPC and AI</div>
<div>- Experience in porting scientific kernels and applications to state-of-the-art CGRAs (e.g., weather/climate codes, CFD, MD, etc.)</div>
<div>- The use of CGRA frameworks (e.g., CGRA-ME and OpenCGRA) to generate and customize architectures</div>
<div>- Software-programmable CGRAs (e.g., Xilinx ACAP Versal)</div>
<div>- Processors with a tightly interconnected CGRA subsystem </div>
<div>- Machine Learning applications and case studies, performance and power-efficiency comparisons between traditional systems (CPUs/GPUs) and CGRAs</div>
<div>- Combination of CGRAs and other emerging post-Moore models (e.g., neuromorphic systems) </div>
<div>- New emerging CGRA-like architectures for Generative AI</div>
<div>- Case studies and evaluations of CGRAs for (Generative) AI</div>
<div>- (New) AI and Machine Learning applications and case studies, performance and power-efficiency comparisons between traditional systems (CPUs/GPUs) and CGRAs</div>
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<div>-------------------------- SUBMISSION ------------------------------</div>
<div>We welcome authors to contribute full-length research papers subject to the topics of interest described above. Contributions should be unpublished and not for consideration in other venues. We will adopt a single-blind review process for </div>
<div>all papers. Papers should not exceed eight (8) single-spaced pages, formatted in the double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style). Accepted papers will be included in the workshop proceedings, </div>
<div>that will be distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.</div>
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<div>We also welcome presentations on new and emerging CGRA technologies from industry and startups. These will be presented at a special lightning session in the workshop. Please contact the workshop organizers (podobas@kth.se) if you </div>
<div>are interested in participating in this event.</div>
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<div> ----------------------- ORGANIZATION -------------------------</div>
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<div>ORGANIZERS:</div>
<div> Artur Podobas (KTH, Sweden)</div>
<div> Kentaro Sano (RIKEN, Japan)</div>
<div> Jason Anderson (University of Toronto, Canada)</div>
<div> Tomohiro Ueno (RIKEN, Japan)</div>
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