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<div>The Third International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing (CGRA4HPC'24)</div>
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<div> ----------------------- GENERAL INFORMATION -------------------------</div>
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<div>CGRA4HPC 2024 will be held in conjunction with IPDPS 2024</div>
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<div><b>Where:</b> San Francisco, CA, USA</div>
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<div><b>Website:</b> http://cgra4hpc.podobas.net/</div>
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<div><b>Submission Link:</b> <a href="https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=CGRA4HPCWorkshopFullSubmission&site=ipdps2024" class="OWAAutoLink" id="LPlnk203048">
https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=CGRA4HPCWorkshopFullSubmission&site=ipdps2024</a></div>
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<div><b>Important Deadlines</b></div>
<div> Paper submission: February 1st, 2024</div>
<div> Paper notification: February 26th, 2024</div>
<div> Camera-ready due: March 15th, 2024</div>
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<div>-------------------------- DESCRIPTION ------------------------------</div>
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<div>Coarse-grained reconfigurable arrays (CGRAs) are programmable logic devices that offer plasticity/reconfigurability, albeit at a coarse-grained (word-configurable) level in comparison to fine-grained FPGAs. <span style="font-size: 12pt;">Such reconfigurability
allows the silicon to be specialized towards a particular application in order to reduce data movement and improve performance and energy efficiency. Unlike their cousins, the Field-Programmable Gate Arrays (FPGAs),</span><span style="font-size: 12pt;"> CGRAs
provide reconfigurable Arithmetic Logic Units (ALUs) and a highly specialized yet versatile data path. This ``coarsening'' of reconfiguration allows CGRAs to achieve a significant (custom ASIC-like) reduction in power consumption and</span><span style="font-size: 12pt;"> increase
in operating frequency compared to FPGAs. At the same time, they remedy and overcome the expensive von Neumann (instruction-decoding) overhead that traditional general-purpose processors (CPUs) suffer from. In short, CGRAs</span><span style="font-size: 12pt;"> strike
a seemingly perfect balance between the reconfigurability of FPGAs and the performance of CPUs, with power consumption characteristics closer to custom ASICs.</span></div>
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<div>The International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing (CGRA4HPC) aspires to provide a recurring forum for HPC experts, users and CGRA hardware researchers from academia or industry <span style="font-size: 12pt;">to
come together and discuss state-of-the-art CGRA research for use in emerging HPC systems.</span></div>
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<div> ----------------------- TOPICS OF INTEREST -------------------------</div>
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<div>Topics of interest include (but are not limited to):</div>
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<div>* CGRA Hardware and Architectures</div>
<div> - Novel high-performance CGRA architectures for use in HPC</div>
<div> - Energy-efficient architectures (incl. asynchronous/clockless </div>
<div> CGRAs, power-consumption optimizations, etc.) </div>
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<div>* Hybrid Processor/CGRA Technology</div>
<div> - Software-programmable CGRAs (e.g., Xilinx ACAP Versal)</div>
<div> - Processors with a tightly interconnected CGRA subsystem</div>
<div> - Combination of CGRAs and other emerging post-Moore models (e.g., neuromorphic systems)</div>
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<div>* Programming Models, Compilers, and Middleware</div>
<div> - Parallel programming language support for programming CGRA </div>
<div> architectures (e.g., supporting OpenMP or CUDA/HIP for </div>
<div> programming CGRA architectures)</div>
<div> - Compilation strategies, algorithms, and methods for mapping </div>
<div> computations and applications onto modern CGRA architectures</div>
<div> - Smart middleware and runtime systems for support of CGRAs, </div>
<div> including multi-CGRA systems for HPC</div>
<div> - The use of CGRA frameworks (e.g., CGRA-ME and OpenCGRA) to generate and customize architectures</div>
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<div>* Use-Cases and Experiments</div>
<div> - Experience in porting scientific kernels and applications to </div>
<div> state-of-the-art CGRAs (e.g., weather/climate codes, CFD, MD, </div>
<div> etc.)</div>
<div> - Machine Learning applications and case studies, performance </div>
<div> and power-efficiency comparisons between traditional systems </div>
<div> (CPUs/GPUs) and CGRAs</div>
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<div>* CGRAs and Generative Artificial Intelligence <b>(NEW for CGRA4HPC'</b><b style="font-size: 12pt;">24)</b></div>
<div> - New emerging CGRA-like architectures for Generative AI</div>
<div> - Case studies and evaluations of CGRAs for (Generative) AI</div>
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<div>-------------------------- SUBMISSION ------------------------------</div>
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<div>We welcome authors to contribute full-length research papers on the topics of interest described above. Contributions should be unpublished and not for consideration in other venues. We will adopt a single-blind review process for <span style="font-size: 12pt;">all
papers. Papers should not exceed eight (8) single-spaced pages, formatted in double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style). Accepted papers will be included in the workshop proceedings, </span><span style="font-size: 12pt;">which
will be distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.</span></div>
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<div>We also welcome presentations on new and emerging CGRA technologies from industry and startups. These will be presented at a special lightning session in the workshop. Please contact the workshop organizers (podobas@kth.se) if you <span style="font-size: 12pt;">are
interested in participating in this event.</span></div>
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<div> ----------------------- ORGANIZATION -------------------------</div>
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<div><b>ORGANIZERS:</b></div>
<div> Artur Podobas (KTH, Sweden)</div>
<div> Kentaro Sano (RIKEN, Japan)</div>
<div> Jason Anderson (University of Toronto, Canada)</div>
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<div><b>PROGRAM COMMITTEE:</b></div>
<div> Ahmed Hemani (KTH, Sweden)</div>
<div> Ahsan Javed Awan (Ericsson, Sweden)</div>
<div> Boma Adhi (RIKEN, Japan)</div>
<div> Cheng Tan (Microsoft, USA)</div>
<div> Jens Domke (RIKEN, Japan)</div>
<div> Lingli Wang (Fudan University, China)</div>
<div> Markus Weinhardt (HS-Osnabrueck, Germany)</div>
<div> Nakashima Yasuhiko (NAIST, Japan)</div>
<div> Takuya Kojima (Univ. of Tokyo, Japan)</div>
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