[IPDPS] CFP: Reconfigurable Architectures Workshop (RAW) 25th Anniversary at IPDPS 2018 - Abstract Deadline 1/12/2018

[Brian Veale]

CALL FOR PAPERS

The 25th Anniversary of the Reconfigurable Architectures Workshop
RAW 2018

May 21-22, 2018
JW Marriot Parq Vancouver
Vancouver, British Columbia, Canada

QUICK LINK: Web site: http://raw.necst.it/

IMPORTANT DATES:

Abstract submission     January 12, 2018
Submission deadline    January 19, 2018
Decision notification     February 16, 2018
Camera-Ready papers due    March 9, 2018


The 25th Reconfigurable Architectures Workshop (RAW 2018) will be held in
Vancouver, British Columbia CANADA in May 2018. RAW 2018 is associated with
the 32nd Annual IEEE International Parallel & Distributed Processing
Symposium (IEEE IPDPS 2018) and is sponsored by the IEEE Computer Society
and the Technical Committee on Parallel Processing. The workshop is one of
the major meetings for researchers to present ideas, results, and on-going
research on both theoretical and practical advances in Reconfigurable
Computing.

A reconfigurable computing environment is characterized by the ability of
underlying hardware architectures or devices to rapidly alter (often on the
fly) the functionalities of their components and the interconnection
between them to suit the problem at hand. The area has a rich theoretical
tradition and wide practical applicability. There are several commercially
available reconfigurable platforms (FPGAs and coarse-grained devices) and
many modern applications (including embedded systems and HPC) use
reconfigurable subsystems. An appropriate mix of theoretical foundations
and practical considerations, including algorithms architectures,
applications, technologies and tools, is essential to fully exploit the
possibilities offered by reconfigurable computing. The Reconfigurable
Architectures Workshop aims to provide a forum for creative and productive
interaction for researchers and practitioners in the area.
_______________________
SUBMISSION OF PAPERS

All manuscripts will be reviewed by at least three members of the program
committee. Submissions should be a complete manuscript or, in special
cases, may be a summary of relevant work. Manuscript for full paper should
be not exceed 8 single-spaced, double-column pages using 10-point size font
on 8.5X11 inch pages (IEEE conference style) including references, figures
and tables. Manuscript for short papers should be not exceed 4
single-space, double-column pages.

Papers are to be submitted through EasyChair. Submitted papers should not
have appeared in or be under consideration for a different workshop,
conference or journal. It is also expected that all accepted papers
(regular or short) will be presented at the workshop by one of the authors.

All papers must be submitted electronically in PDF format.

Submissions can be made through:
. the RAW2018 web site: http://raw.necst.it/
. EasyChair: https://easychair.org/conferences/?conf=raw2018
_________________
IMPORTANT DATES

Astract submission January 12, 2018
Submission deadline January 19, 2018
Decision notification February 16, 2018
Camera-Ready papers due March 9, 2018

___________________
TOPICS OF INTEREST

Architectures & CAD

Algorithmic Techniques and Mapping

Emerging Technologies (optical models, 3D Interconnects, devices)
Reconfigurable Accelerators
Embedded systems and Domain-Specific solutions (Digital Media, Gaming,
Automotive applications)
FPGA-based MPSoC and Multicore
Distributed Systems & Networks
Wireless and Mobile Systems
Critical issues (Security, Energy efficiency, Fault-Tolerance)


Hot Topics in Reconfigurable Computing

Configurable Cloud
Heterogeneous Computing in Data Centers
Accelerating Data Center Workloads
FPGA-based Deep Learning
Accelerating Genomic Computations
Acceleration of Data Analytics
Reconfigurable Computing in the IoT era
Organic Computing, Biology-Inspired Solutions
Applications in Finance


Runtime & System Management

Run-Time Reconfiguration Models and Architectures
Autonomic computing systems
Operating Systems and High-Level Synthesis
High-Level Design Methods (Hardware/Software co-design, Compilers)
System Support (Soft processor programming)
Runtime Support
Reconfiguration Techniques
Simulations and Prototyping (performance analysis, verification tools)

____________
ORGANIZERS

Workshop Chairs

Dirk Stroobandt, Ghent University, Belgium
Ken Eguro, Microsoft Research


Program Chairs

Marco D. Santambrogio, Politecnico di Milano, Italy
Diana Goehringer, TU Dresden, Germany


Steering Committee

Juergen Becker, Karlsruhe Insttute of Technology, Germany
Viktor K. Prasanna, University of Southern California, USA
Ramachandran Vaidyanathan, Louisiana State University, USA


Steering Chair

Viktor K. Prasanna, University of Southern California, USA


Publicity

Brian Veale, IBM, USA
Ivan Beretta, University of Westminster, UK
Laura Nacci, Politecnico di Milano, Italy


Webmaster and submission Chair

Marco Rabozzi, Politecnico di Milano, Italy
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://ipdps.org/pipermail/announce_ipdps.org/attachments/20171214/56a8c0bd/attachment.html>